1. Field of the Invention
The present invention relates to a liquid crystal display device and a method for fabricating the same, and more particularly, to an array substrate for in-plane switching (IPS) mode liquid crystal display device and a method for fabricating the same.
2. Discussion of the Related Art
In general, a liquid crystal display (LCD) device uses optical anisotropy and polarization properties of liquid crystal molecules to create images, and the liquid crystal molecules have a natural alignment order. In addition, the alignment order of the liquid crystal molecules can be altered by an electric field, such that the alignment order of the liquid crystal molecules changes as the direction of the electric field being applied to the liquid crystal molecules changes. Accordingly, by applying an electric field to the liquid crystal molecules, light incident on the liquid crystal molecules is then refracted by the changes in the alignment order of the liquid crystal molecules to thereby display images in the LCD device.
Further, thin film transistors and pixel electrodes are generally employed to create the electric field being applied to the liquid crystal molecules. The thin film transistors and the pixel electrodes are commonly arranged in a matrix in a LCD device, often referred to as an active matrix LCD device, because the matrix arrangement controls the size of a pixel to thereby provide a high resolution in display images and how quickly each pixel changes to thereby provide superiority in displaying moving images.
FIG. 1 is a planar view of an array substrate for an IPS mode LCD device according to related art. In FIG. 1, a gate line 12 and a common line 16 are formed spaced apart from each other along a first direction on an array substrate 10. A data line 24 is formed along a second direction perpendicular to the first direction and a pixel region P is defined by the gate and data lines 12 and 14 crossing with each other. Also a pixel electrode 30 and a thin film transistor T are formed within the pixel region P on the array substrate 10. The thin film transistor T is switched by signals of the gate line 12 to transfer signals of the data line 14 to the pixel electrode 30. In particular, the thin film transistor T includes a gate electrode 14 extended from the gate line 12, an active layer 20 covering the gate electrode 14, and source and drain electrodes 26 and 28 spaced apart from each other. The source and drain electrodes 26 and 28 are formed over the active layer 20, such that the source electrode 26 is extended from the data line 24 and the drain electrode 28 connects to the pixel electrode 30. Also the pixel electrode 30 includes a horizontal portion 30a extended from the drain electrode 28, and a plurality of vertical portions 30b extended from the horizontal portion 30a. 
In addition, a common electrode 17 is formed within the pixel region P and connects to the common line 16 on the array substrate 10. The common electrode 17 is parallel to the pixel electrode 30. Further, the common electrode 17 includes a horizontal portion 17a and a plurality of vertical portions 17b, which vertically extend from the horizontal portion 17a and the common line 16. Moreover, the vertical portions 17b of the common electrode 17 interpose between the plurality of vertical portions 30b of the pixel electrode 30. The array substrate 10 also includes a storage capacitor CST formed by the overlapping of the horizontal portion 17a of the common electrode 17 and the horizontal portion 30a of the pixel electrode 30, such that the storage capacitor CST is electrically connected to a liquid crystal capacitor CLC (not shown) in the pixel region P. In particular, the horizontal portion 17a of the common electrode 17 serves as a first storage electrode of the storage capacitor CST, and the horizontal portion 30a of the pixel electrode 30 serves as a second storage electrode of the storage capacitor CST.
According to the related art, the vertical portion 17b of the common electrode 17 adjacent to the data line 24 has a larger width than the other vertical portions 17b in order to protect liquid crystal molecule materials adjacent to the data line 24 from being affected by signals flowing through the data line 24. However, because the data line 24 crosses over the gate line 12 and the common line 16, a deposition state at portions near the data line 24 is unstable and the data line 24 may be easily broken.